Capacitor is an electronic component that stores electric charge. In a conventional fabrication process, realization of a physically large capacitor on an integrated circuit is very costly unless special fabrication process steps have been added to implement it. Real physical capacitors with capacitance values higher than 100 pF are considered to be a physically large capacitor with unfeasible manufacturing costs. Therefore, such a physically large capacitor construction should be avoided. One solution of this problem is to employ a Capacitance Multiplier circuit in place of a real physical capacitor with excessively large capacitance value.
Capacitance multipliers can be grouped as voltage-based capacitance multipliers (e.g. Miller multipliers) and current-based capacitance multipliers.
A Miller capacitance multiplier senses a voltage through the capacitor and feeds back a voltage. A Miller capacitance multiplier requires adding additional power and circuitry such as a trans-impedance amplifier which affects the frequency response of the overall amplifier circuit. The frequency response stability of the overall circuit may be adversely affected.
In a current-based capacitance multiplier, a current through a capacitor is sensed, multiplied and fed back. In a conventional example, the multiplier circuit senses current and multiplies the current while mirroring back the current to an input node.
For example, U.S. Pat. No. 3,911,296 discloses a capacitance multiplier which comprises an integrated (Miller) capacitor structure coupled between the collector and base electrodes of an integrated NPN transistor. Effective capacitance is produced between the collector and ground having a value of Cx=(β+1) C where is the transistor current gain, C is the Miller Capacitance. One apparent disadvantage of the circuit described by U.S. Pat. No. 3,911,296 is that the resultant capacitance is a function of the beta of the transistor which itself is process and temperature dependent. Thus, the value of the effective capacitance varies strongly due to process and temperature variations. Another disadvantage of the circuit of U.S. Pat. No. 3,911,296 is that on-chip capacitor takes up die area of the integrated circuit chip. In large scaled integrated circuits, the useable area of the integrated circuit chip becomes quite important such that elimination of the need to assign a portion of the area to fabricate “on-chip” capacitors can be a significant advantage to the circuit designer.
Some previous applications of Capacitor Multipliers in the art (such as U.S. Pat. No. 3,831,117 to Fletcher et. al) involves the employment of operational amplifiers as the active element. FIG. 1A displays an example of this kind of capacitance multiplier circuit. The circuit 1 is based on operational amplifier 20, two resistors 2, 3 and a reference capacitor 11. This circuit 1 has the advantage of using single active element (Op-amp) but has a disadvantage of being far from pure capacitance simulator.
Equivalent impedance between terminal a of this circuit 1 and ground G equals to a series connected RC circuit consisting of lossless capacitor 4 and lossy component 5, as shown in FIG. 1B. Therefore, this circuit can only simulate a lossy capacitance. This is apparent from the input impedance which is of the form
                              Z          i                =                                                                              R                  1                                ⁢                                  R                  2                                                                              R                  1                                +                                  R                  2                                                      +                                          R                2                                            j                ⁢                                                                  ⁢                ω                ⁢                                                                  ⁢                                  C                  ⁡                                      (                                                                  R                        1                                            +                                              R                        2                                                              )                                                                                =                                    R              x                        -                          jX              c                                                          (                  Equation          ⁢                                          ⁢          1                )            where C is the actual (physical) capacitance which is to be amplified j is the basic complex number (square root of minus 1), and ω is the angular frequency. All of these terms are well known by those who are specialized in the art.
This equation tells us that equivalent impedance consists of a series connected resistance and a capacitive reactance. Multiplier term is
                    k        =                              R            2                                              R              1                        +                          R              2                                                          (                  Equation          ⁢                                          ⁢          2                )            and it equally applies to resistor R1 and capacitor C, therefore yields a lossy form of a capacitance multiplier.
It should be pointed out that the resistor connected to inverting terminal of the op-amp in FIG. 1 of U.S. Pat. No. 3,831,117 has no effect on the circuit driving point impedance, and FIG. 1 presented herein differs in that sense.
More recent articles published in scientific and technical literature, and newer patents focus on modifying operational amplifier based designs of C-multipliers. For example, a C-multiplier circuit proposed by Smith et. al in U.S. Pat. No. 7,466,175 B2 is based on an opamp in conjunction with a current mirror circuit. The input of the current mirror arrangement senses the current through a small reference capacitor. The output of the current mirror arrangement is connected in parallel with the reference capacitor. The overall arrangement forms a capacitance multiplier with a multiplication factor of N+1, where N is the current gain or current gain factor of the current mirror arrangement.
Another U.S. Pat. No. 8,816,760 B2, awarded to Sung, 2014) teaches us how to implement current mirror structures and a couple of current sources to improve a C-multiplier performance in connection with an operational amplifier element. On the other hand, lossy C-multipliers involve many unwanted parasitic terms and noise sources which increase by thermal agitation. These become strongly disturbing and deteriorate the performance of monolithic integrated circuits.
Elimination of lossy terms can be possible only using additional active elements (for example, two operational amplifiers are used in U.S. Patent 20070090872 A1 2007 by Y-C Chen, Y-C Lu), however, at the cost of circuit complexity, and increased chip area.
Many previous art. C-multipliers are prone to failure in one or more of the following issues: Use of two or more active elements (such as opamps), excessive use of passive components and circuit extensions such as current mirrors or current sources in connection with the main active element, narrow bandwidth, low frequency restrictions due to parasitics, and lossy terms.
A circuit to be used for the purpose should employ minimum number of active and passive elements which is important from the point of view of integrated circuit implementation, power consumption, cost and area on the chip. Realizations of said structures would preferably be canonic in the number of passive components and do not require any critical component matching condition. After all, it will be apparent for those who are specialized in the art that the circuits presented herein fulfill these requirements.
Negative Capacitance Multipliers:
Negative capacitance multipliers (simulators) (NCM) have applications in capacitive cancellation schemes and frequency bandwidth extension techniques and to devise various filters and oscillators. Fundamental circuit topologies of NCMs are known as Negative impedance convertors (NICs).
D. J. Comer et al. describe such applications in “Bandwidth extension of high-gain CMOS stages using active negative capacitance”, in Proceedings of 13th IEEE International Conference on Electronics, Circuits and Systems pp. 628-631, 2006. One of the best known previous art was reported by A. Antoniou, wherein the realized floating NIC required two op-amps and five resistors and required resistor matching “Floating negative impedance converter”, IEEE Trans. CT-19, 209-212, 1972. Floating negative capacitance simulators using different active elements have been reported by R. Senani in “Floating GNIC/GNII configuration with only a single OMA”. Electron. Lett. 35(6), 423-425, 1995, E. Yuce has reported several NICs for simulating grounded negative capacitors in “A modified CFOA and its applications to simulated inductors, capacitance multipliers, and analog filters”, IEEE Transactions on Circuits and Systems I, 55(1), 266-275, February 2008. A paper by M. T. Abuelma'atti and S. K. Dhar introduces a circuit of a floating type negative capacitance circuit with 2 CFOAs and 3 passive elements in “New CFOA based floating immittance emulators”, International Journal of Electronics, 103, 12, 1984-1997, 2016. A. Lahiri and M. Gupta have presented negative capacitance circuits using CFOAs in “Realizations of Grounded Negative Capacitance Using CFOAs”, Circuits Systems and Signal Processing 30: 143-155, 2011. The negative C-multiplier circuit presented in FIG. 5 (circuit D in “Realizations of Grounded Negative Capacitance Using CFOAs”. Circuits Systems and Signal Processing 30: 143-155, 2011) of Lahiri and Gupta provides an ideal negative capacitance value of
                              C          eq                =                              -            C                    ⁢                                    R              2                                      2              ⁢                                                          ⁢                              R                1                                                                        (                  Equation          ⁢                                          ⁢          3                )            
However, r non-ideal conditions this becomes
                                          C            eq                    =                                    -              C                        ⁢                                                            R                  2                                -                                  R                  x                                                            2                ⁢                                  R                  1                                                                    ,                              R            eq                    =                      -                                                            R                  1                                ⁢                                  R                  x                                                                              R                  2                                -                                  R                  x                                                                                        (                  Equation          ⁢                                          ⁢          4                )            
In other words, a parasitic resistance term is included in ideal negative capacitance equation, and negative resistance term is included in the input impedance equation of their proposed circuit.
So far, none of previous art C-multipliers have implemented Y terminal of the CFOA in grounded form. Therefore, no matter if they are positive or negative C-multipliers, they all suffer similar problems of the above given example circuit of previous art. Moreover, they are prone to deviate strongly from ideal under certain circumstances. For instance, in the above cited previous art circuit of “Realizations of Grounded Negative Capacitance Using CFOAs”, A. Lahiri and M. Gupta, Circuits Systems and Signal Processing 30: 143-155, 2011, R2=RX becomes critical condition. It has been observed that deviation from ideal capacitance can be more severe for some other previous art circuits.
Current Feedback Amplifiers:
Operational Amplifiers (opamps) are widely used and well known building blocks. From the circuit theory point of view, an opamp is modeled by a voltage controlled voltage source (VCVS) which accepts voltages as their input.
By using a different architecture for the input stage of the operational amplifier, which accepts currents as their input, a substantial improvement in their performance may be achieved and this structure is named as current feedback operational, amplifier (CFOA) also known as the trans-impedance operational amplifiers.
Symbolic representation of a CFOA 14 is shown in FIG. 2A. Internal structure of a CFOA 14 comprises a CCII (second generation current conveyor) 6 which can be either one of a positive or negative type, and an output buffer stage 7, as shown in FIG. 2B. The CFOA is a four-terminal active building block and described by the following matrix equation,
                              [                                                                      V                  x                                                                                                      I                  y                                                                                                      I                  z                                                                                                      V                  W                                                              ]                =                              [                                                            0                                                  1                                                  0                                                  0                                                                              0                                                  0                                                  0                                                  0                                                                                                  ±                    1                                                                    0                                                  0                                                  0                                                                              0                                                  0                                                  1                                                  0                                                      ]                    ⁡                      [                                                                                I                    x                                                                                                                    V                    y                                                                                                                    V                    z                                                                                                                    V                    w                                                                        ]                                              (                  Equation          ⁢                                          ⁢          5                )            
The input signal of an (ideal) current conveyor is current; therefore, the input impedance at terminal X of an ideal CFOA is zero. The Y terminal (the non-inverting input of said element) has very high input impedance. The two outputs Z and W have very high and very low output impedance, respectively.
U.S. Pat. No. 7,388,432 B1 (2008) by Gert Jan van Sprakelaar teaches on Current feedback amplifiers with extended common mode input range. Recently, an integrated, fully-differential current feedback trans impedance operational amplifier circuit is disclosed in U.S. Pat. No. 9,236,841 B2 (2016) by Ciubotaru.
CFOA Based Capacitance Multipliers of Previous Art:
Although there are many examples of grounded and floating inductors published in literature related to the application of CFOAs, there are only few papers related to CFOA based emulations of grounded C-multipliers.
Inspection of these earlier works related to said subject shows that; the circuit presented in FIG. 4, 33a in the book published b R. Senani et, al, employs 5 passive components and a CFOA and has a serious drawback of necessitating component, matching of two resistors and two capacitors used in the circuit in “Current Feedback Operational Amplifiers and Their Applications”, Springer Science and Business Media, New York 2013. A paper by M. T. Abuelma'atti and S. K. Dhar of “New CFOA based floating immittance emulators”, International Journal of Electronics, 103, 12, 1984-1997, 2016, and a recent U.S. Pat. No. 9,548,721, 17 Jan. 2017, introduces both lossless and lossy floating capacitance emulators employing three CFOAs and three passive components. R. Arslanalp and T. Yucehan describe a grounded CFOA-based capacitance multiplier, with a negative relationship between input and compensation terminal currents in “Capacitance multiplier design by using CFOA”, 23rd Signal Processing and Communications Applications Conference (SIU), 16-19 May 2015. Their report on circuit simulation results reveals that said circuit has large capacitance deviations for increased values of multiplier coefficients. A paper by A. Khan et. al. presents a C-multiplier using a CFOA in “Current conveyor based R and C-multiplier circuits”. AEU, Int. J. Electron. Commun. 56 (5), 312-316, 2002. However, it includes an additional current conveyor element, therefore is not a (minimal) single CFOA based circuit.